Energy and peak-current per-cycle estimation at RTLGUPTA, Subodh; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 4, pp 525-537, issn 1063-8210, 13 p.Article

Prelayout estimation of individual wire lengthsBODAPATI, Srinivas; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 6, pp 943-958, issn 1063-8210Article

Power-aware technology mapping for LUT-based FPGAsANDERSON, Jason H; NAJM, Farid N.IEEE international conference on field-programmable technology. 2002, pp 211-218, isbn 0-7803-7574-2, 8 p.Conference Paper

Low-Power Programmable FPGA Routing CircuitryANDERSON, Jason H; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 8, pp 1048-1060, issn 1063-8210, 13 p.Article

Power estimation for large sequential circuitsKOZHAYA, Joseph N; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 2, pp 400-407, issn 1063-8210Article

Statistical timing analysis with two-sided constraintsHELOUE, Khaled R; NAJM, Farid N.IEEE/ACM International Conference on Computer-Aided Design. 2005, pp 829-836, isbn 0-7803-9254-X, 1Vol, 8 p.Conference Paper

Low power VLSI design and technologyYEAP, Gary K; NAJM, Farid N.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, 122 p.Serial Issue

Low-leakage asymmetric-cell SRAMAZIZI, Navid; NAJM, Farid N; MOSHOVOS, Andreas et al.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 4, pp 701-715, issn 1063-8210, 15 p.Article

Low-power programmable routing circuitry for FPGAsANDERSON, Jason H; NAJM, Farid N.IEEE/ACM International Conference on Computer-Aided Design. 2004, isbn 0-7803-8702-3, 2Vol, vol2, 602-609Conference Paper

Power estimation techniques for FPGAsANDERSON, Jason H; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 10, pp 1015-1027, issn 1063-8210, 13 p.Conference Paper

A technique- for improving dual-output domino logicRAMPRASAD, Sumant; HAJJ, Ibrahim N; NAJM, Farid N et al.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 4, pp 508-511, issn 1063-8210, 4 p.Article

Dynamic range estimation for nonlinear systemsBIN WU; JIANWEN ZHU; NAJM, Farid N et al.IEEE/ACM International Conference on Computer-Aided Design. 2004, isbn 0-7803-8702-3, 2Vol, vol2, 660-667Conference Paper

A novel low-power FPGA routing switchANDERSON, Jason H; NAJM, Farid N.Custom integrated circuits conference. 2004, pp 719-722, isbn 0-7803-8495-4, 1Vol, 4 p.Conference Paper

Incremental partitioning-based vectorless power grid veificationKOUROUSSIS, Dionysios; FERZLI, Imad A; NAJM, Farid N et al.IEEE/ACM International Conference on Computer-Aided Design. 2005, pp 358-364, isbn 0-7803-9254-X, 1Vol, 7 p.Conference Paper

Introduction to low-power VLSI designYEAP, G; WILD, A.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 223-248Article

A case for asymmetric-cell cache memoriesMOSHOVOS, Andreas; FALSAFI, Babak; NAJM, Farid N et al.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 7, pp 877-881, issn 1063-8210, 5 p.Article

Statistical timing analysis based on a timing yield modelNAJM, Farid N; MENEZES, Noel.Design automation conference. 2004, pp 460-465, isbn 1-58113-828-8, 6 p.Conference Paper

Variations-aware low-power design and block clustering with voltage scalingAZIZI, Navid; KHELLAH, Muhammad M; DE, Vivek K et al.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 7, pp 746-757, issn 1063-8210, 12 p.Article

Low power design of off-chip drivers and transmission lines : A branch and bound approachGUPTA, R; WILLIS, J; PILEGGI, L. T et al.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 249-267Article

A new CMOS driver model for transient analysis and power dissipation analysisLIAO, H; WAYNE WEI-MING DAI; WANG, R et al.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 269-285Article

Retiming sequential circuits for low powerMONTEIRO, J; DEVADAS, S; GHOSH, A et al.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 323-340Article

Floorplan design with low power considerationsCHAO, K.-Y; WONG, D. F.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 305-322Article

An analytical approach for dynamic range estimationBIN WU; JIANWEN ZHU; NAJM, Farid N et al.Design automation conference. 2004, pp 472-477, isbn 1-58113-828-8, 6 p.Conference Paper

On the optimal drivers of high-speed low power ICsZHOU, D; LIU, X. Y.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 287-303Article